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High-Frequency Trading Using External DRAM
 Nevrkla, Lukáš ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
The primary part of low-latency trading is a machine that can trade with lower latency than any other trader. Hardware-accelerated platforms can reduce trading latency down to hundreds of nanoseconds. This work focuses on a specific data structure (Order Book) inside this hardware platform that manages the current market price levels. The current implementation manages this data structure inside the software of the hosting machine, and only a few best price levels are inside the hardware. Synchronization between hardware and software has a latency in the order of microseconds. Therefore the best price levels are sometimes unavailable inside the hardware platform. This work presents a solution for managing this structure inside FPGA while saving its content inside the external dynamic memory. The new solution reduces the latency down to 150–200 nanoseconds with occasional (2 % cases) increase to 450–650 nanoseconds. Lower latency will help the trading platform react faster to larger stock market changes which are very important for traders.
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